A conventional semiconductor test equipment is comprised of a circuit configuration as shown in FIG. 2. The conventional semiconductor test equipment 1 has a clock generator 2, a pattern generator 20, a wave formatter 3, a driver 5, a logic comparator 4 and an analog comparator 6. As shown in FIG. 2, a set of these circuit components are provided for each device pin 19 of a semiconductor device 7 to be tested. Thus, in an actual semiconductor test equipment 1, a large number of sets of circuit components are provided to meet the needs of testing the semiconductor device 7 having a large number of device pins.
The pattern generator 20 generates a test pattern signal and a reference pattern signal in response to the reference clock from the clock generator 2. The test pattern signal is provided to the wave formatter 3 wherein it is formatted to a predetermined waveform such as a non-return zero (NRZ) signal, a return-zero (RZ) signal or an exclusive OR (EOR) signal as is well known in the art. The test pattern signal from the wave formatter 3 is applied to the corresponding device pin 19b of the device under test 7 through the driver 5 which determines an amplitude and a slew rate of the test pattern signal.
The analog comparator 6 receives the output signal from the device pin 19b which is resulted in response to the test pattern signal and compares the output signal with a reference voltage (not shown) to determine whether the output signal from the pin 19b is logical "1" or "0 ". The logic comparator 4 compares the output of the analog comparator 6 with the reference pattern from the pattern generator 20 to determine whether the logic of the pin 19b agrees with the reference logic signal. If the output of the device pin 19a does not agree with the reference signal, the logic comparator 4 generates a fail signal.
The other pin 19c of the device under test 7 receives the test pattern signal through another set of the pattern generator 20, wave formatter 3 and the driver 5 and returns the resulted signal to another set of the analog comparator 6 and the logic comparator 4. In a similar manner, each of the other sets of circuit components in the semiconductor test equipment 1 is arranged to accommodate each of the other pins 19c-19n of the device under test 7.
Parameters of each test signal to be applied to each device pin of 19a, 19b, . . . 19n of the DUT 7 includes a time period, a voltage, a current. The parameters for each pin 19 of the DUT 7 are usually different from one another and have to be adjusted depending on the characteristics of the device 7 and the purpose of the test.
In the conventional semiconductor test equipment, all of these circuit components are designed to provide the highest possible performance to test a wide range of semiconductor devices. For example, the pattern generators 20 and the wave formatters 3 have the highest performance, i.e., an ability to generate and wave-shape the test pattern the frequency of which is high enough to fully evaluate devices in the market having a highest operating frequency. The drivers 5, for example, have been designed to drive the test pattern with the widest voltage or current swings required for testing devices which is to operate in the largest amplitude. The analog comparators 6 and the logic comparators 4 have also been designed to meet the highest frequency requirement for testing the devices of the highest operating frequency.
Therefore, the cost of the circuit components in the conventional semiconductor equipment of FIG. 2 becomes considerably high and the size of such circuit components tends to increase. Furthermore, the density and performance of recent semiconductor devices are ever increasing. For example, some recent large scale integrated circuits have a large number of pins up to 256 or 512 or more. Accordingly, for testing such devices, the semiconductor test equipment has to install the corresponding sets of circuit components therein. One of the most recent semiconductor test equipment includes 1,000 sets of the circuit components to accommodate a semiconductor device having 1000 pins, which extremely increases the cost of the test equipment.
Therefore, in the conventional semiconductor test equipment of FIG. 2, the cost and size of the circuit components increases with increase of the device capability and the number of device pins.